pc電源中PWR_OK的作用是什么?
PC電源中PWR_OK的作用到底是什么?我在網(wǎng)上看網(wǎng)友們說是給主板信號說明電源已經(jīng)OK.但在實(shí)際中發(fā)現(xiàn)把PWR_OK這根線剪斷,主板也照常起動. 實(shí)測主板端PWR_OK腳有5V電壓,我對主板不是很了解,請問這是什么原因?
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PS_ON# is an active-low, TTL-compatible signal that allows a motherboard to remotely
control the power supply in conjunction with features such as soft on/off, Wake on LAN*,
or wake-on-modem. When PS_ON# is pulled to TTL low, the power supply should turn
on the four main DC output rails: +12VDC, +5VDC, +3.3VDC and -12VDC. When
PS_ON# is pulled to TTL high or open-circuited, the DC output rails should not deliver
current and should be held at zero potential with respect to ground. PS_ON# has no effect
on the +5VSB output, which is always enabled whenever the AC power is present. Table
16. lists PS_ON# signal characteristics.
The power supply shall provide an internal pull-up to TTL high. The power supply shall
also provide de-bounce circuitry on PS_ON# to prevent it from oscillating on/off at startup
when activated by a mechanical switch. The DC output enable circuitry must be SELVcompliant.
The power supply shall not latch into a shutdown state when PS_ON# is driven active by
pulses between 10ms to 100ms during the decay of the power rails.
control the power supply in conjunction with features such as soft on/off, Wake on LAN*,
or wake-on-modem. When PS_ON# is pulled to TTL low, the power supply should turn
on the four main DC output rails: +12VDC, +5VDC, +3.3VDC and -12VDC. When
PS_ON# is pulled to TTL high or open-circuited, the DC output rails should not deliver
current and should be held at zero potential with respect to ground. PS_ON# has no effect
on the +5VSB output, which is always enabled whenever the AC power is present. Table
16. lists PS_ON# signal characteristics.
The power supply shall provide an internal pull-up to TTL high. The power supply shall
also provide de-bounce circuitry on PS_ON# to prevent it from oscillating on/off at startup
when activated by a mechanical switch. The DC output enable circuitry must be SELVcompliant.
The power supply shall not latch into a shutdown state when PS_ON# is driven active by
pulses between 10ms to 100ms during the decay of the power rails.
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@萬里毛叔
PS_ON#isanactive-low,TTL-compatiblesignalthatallowsamotherboardtoremotelycontrolthepowersupplyinconjunctionwithfeaturessuchassofton/off,WakeonLAN*,orwake-on-modem.WhenPS_ON#ispulledtoTTLlow,thepowersupplyshouldturnonthefourmainDCoutputrails:+12VDC,+5VDC,+3.3VDCand-12VDC.WhenPS_ON#ispulledtoTTLhighoropen-circuited,theDCoutputrailsshouldnotdelivercurrentandshouldbeheldatzeropotentialwithrespecttoground.PS_ON#hasnoeffectonthe+5VSBoutput,whichisalwaysenabledwhenevertheACpowerispresent.Table16.listsPS_ON#signalcharacteristics.Thepowersupplyshallprovideaninternalpull-uptoTTLhigh.Thepowersupplyshallalsoprovidede-bouncecircuitryonPS_ON#topreventitfromoscillatingon/offatstartupwhenactivatedbyamechanicalswitch.TheDCoutputenablecircuitrymustbeSELVcompliant.ThepowersupplyshallnotlatchintoashutdownstatewhenPS_ON#isdrivenactivebypulsesbetween10msto100msduringthedecayofthepowerrails.
樓上的兄弟,你說的是PS_ON,好像跟PWR_OK不一樣
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@爭鋒
樓上的兄弟,你說的是PS_ON,好像跟PWR_OK不一樣
看錯(cuò)里,哈哈,抄的啊
PWR_OK is a “power good” signal. This signal should be asserted high by the power
supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are within the
regulation thresholds listed in Table 15 and that sufficient mains energy is stored by the
converter to guarantee continuous power operation within specification for at least the
duration specified in Section 3.2.9. Conversely, PWR_OK should be de-asserted to a
low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages falls below
its under voltage threshold, or when mains power has been removed for a time
sufficiently long such that power supply operation cannot be guaranteed. The electrical
and timing characteristics of the PWR_OK signal are given in Table 21 and in Figure 2.
PWR_OK is a “power good” signal. This signal should be asserted high by the power
supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are within the
regulation thresholds listed in Table 15 and that sufficient mains energy is stored by the
converter to guarantee continuous power operation within specification for at least the
duration specified in Section 3.2.9. Conversely, PWR_OK should be de-asserted to a
low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages falls below
its under voltage threshold, or when mains power has been removed for a time
sufficiently long such that power supply operation cannot be guaranteed. The electrical
and timing characteristics of the PWR_OK signal are given in Table 21 and in Figure 2.
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